1. Field of the Invention
The invention relates in general to automated test equipment, and in particular to a system for measuring characteristics of a digital signal including its jitter, analog noise levels, period, frequency, skew, and rise and fall times.
2. Description of Related Art
Digital integrated circuits (ICs) communicate through digital data signals, and when a transmitting IC transmits a digital data signal to a receiving IC, the transmitter typically synchronizes state changes in the digital data signal to leading (or trailing) edges of a periodic clock signal so that the state changes within the data signal will occur at predictable times. To produce a data sequence represented by successive states of the digital signal, the receiver need only digitize the data signal with an appropriate sampling phase and frequency. In some communication systems, a transmitter sending a digital data signal to a receiver also sends a clock signal to the receiver for controlling the timing with which the receiver samples the data signal. In other communication systems the receiver may include a “clock recovery” system for generating the sampling clock signal locally, using a feedback control system to adjust the phase and frequency of the sampling clock signal based on an analysis of data the receiver acquires by observing the data signal.
FIG. 1 depicts the voltage of a typical serial data signal as a function of time. The signal transitions between high and low logic levels VH and VL differ by a nominal peak-to-peak voltage VPP with transitions occurring with a nominal clock period P. While a transmitting IC may synchronize the edges of a data signal to edges of a clock signal having period P, a data signal can often appear somewhat jittery to a receiving IC in that timing with which data signal edges cross a midpoint level midway between VH and VL varies to some extent, for example, due to noise. For example, while edges 10 and 11 cross over the midpoint level at the expected times, noise in edge 12 causes it to cross over the midpoint level too soon. Noise can also cause variation in the signal's logic level as shown at points 14 and 15 in the waveform of FIG. 1.
Variation in signal edge timing (jitter) can be random or deterministic. Random jitter arises from random noise in the transmitting IC or in the signal path conveying the signal to the receiving IC. Noise in the signal path conveying the data signal to the receiving IC can introduce jitter into the data signal. In a system where the transmitter sends a clock signal to the receiver, noise in the clock signal path can also cause the receiving IC to perceive the data signal to be jittery relative to the clock signal. In a receiving IC employing a clock recovery system to generate a local clock signal, feedback errors or noise in the clock recovery system can cause jitter in the clock signal, thereby causing the data signal to appear jittery relative to the clock signal. Random jitter renders the timing of each signal edge somewhat non-deterministic in that is not possible to predict the amount of timing error in any individual signal edge arising from random noise.
Deterministic jitter arises from inherent characteristics of the transmitting and receiving ICs and the signal path interconnecting them. For example all signal paths delay signal edges by an amount that is a function of signal frequency. When a digital data signal conveys a bit pattern such as {01010101 . . . }, it will act as a relatively higher frequency signal than when it conveys a bit pattern such as {00000111110000011111 . . . }. Thus the amount by which a signal path delays an edge of such a signal depends on the particular data pattern the signal currently conveys. This “pattern-dependant” jitter is deterministic in that timing error in each data signal edge due to pattern-dependant jitter for a given pattern is predictable based on the nature of the pattern and on characteristics of the channel hardware. Deterministic jitter that is not pattern-dependant can arise, for example, from periodic noise that is coherent with the clock signal the transmitting IC uses to time edges.
FIG. 2 is a conventional “eye-diagram” generated by a storage oscilloscope repeatedly sweeping a digital signal so that traces of a large number of the signal's data cycles are superimposed on the display. If the signal were not subject to noise or jitter, the signal trace would follow the path indicated by the solid lines of FIG. 2, but due to noise and jitter, the signal trace can move anywhere in the shaded area of FIG. 2.
Since a receiver periodically samples a digital signal between transitions to determine the data sequence it represents, it can tolerate some amount of jitter, but when a digital signal is too jittery, the receiver will not be able to correctly determine each successive state of the digital signal from the samples it acquires because it will sometimes sample the signal to soon or too late. Digital system specifications therefore require that the amount of jitter in a digital signal remain within acceptable limits. One measure of jitter, called “peak-to-peak jitter” corresponds to the width of the shaded area of FIG. 2 at the nominal crossover point 20, representing a difference in relative timing of earliest and latest arriving signal edges. System specifications typically require peak-to-peak jitter to remain within a predetermined limit.
A receiver can also tolerate some amount of noise induced variation in the voltage of its signal logic levels, but when the variation becomes too large, it will not be able to correctly determine the logic level represented by each sample because the signal may sometimes may fail to be on the correct side of the midpoint voltage at the moment the receiver samples it. Digital system specifications therefore require that the amount of voltage variation in a digital signal remain within acceptable limits. For example, some digital system specifications require that difference between the lowest detected high logic level and the highest detected low logic level (the “vertical eye opening” shown in FIG. 2) to be no smaller than some specified minimum.
To determine whether an IC can tolerate a specified amount of jitter or logic level variation, some testers can add a specified amount of jitter to one or more of the IC's input data or clock signals while monitoring the IC's output signals to determine whether the digital output signals exhibit their expected sequences of logic states. It would also be beneficial if an IC tester could also measure the amount of jitter and logical level variation in an IC's digital output signal to determine whether they are within specified limits. It would further be helpful if the tester could also measure other characteristics of a digital signal including, for example, period, skew and rise and fall times.